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Device and Circuit Design for VLSI

Mohsen, Amr (1979) Device and Circuit Design for VLSI. In: Proceedings of the Caltech Conference On Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 31-54. http://resolver.caltech.edu/CaltechCONF:20120504-133742355

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Abstract

A review of the device and circuit design complexity and limitations for VLSI is presented. VLSI device performance will be limited by second order device effects, interconnection line delay and current density and chip power dissipation. The complexity of VLSI circuit design will require hierarchical structured design methodology with special consideration of testability and more emphasis on redundancy. New organizations of logic function architectures and smart memories will evolve to take advantage of the topological properties of the VLSI silicon technology.


Item Type:Book Section
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Computer Science Technical Report3340
Record Number:CaltechCONF:20120504-133742355
Persistent URL:http://resolver.caltech.edu/CaltechCONF:20120504-133742355
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:175
Collection:CaltechCONF
Deposited By: Kristin Buxton
Deposited On:08 Aug 2012 21:52
Last Modified:26 Dec 2012 07:10

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