CaltechCONF
  A Caltech Library Service

A Subnanosecond LSI Family for Mainframe Technology

Muller, H. H. and Stopper, H. and Tam, R. K. (1979) A Subnanosecond LSI Family for Mainframe Technology. In: Proceedings of the Caltech Conference On Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 105-112. http://resolver.caltech.edu/CaltechCONF:20120504-144406140

[img]
Preview
PDF - Published Version
See Usage Policy.

650Kb

Use this Persistent URL to link to this item: http://resolver.caltech.edu/CaltechCONF:20120504-144406140

Abstract

A subnanosecond LSI family is defined for next generation mainframes. It employs distributed on-chip regulation to reduce system power supply cost, stacked structures for delay-power improvement, on-chip test/diagnostic monitors and signature circuits to improve system maintainability.


Item Type:Book Section
Other Numbering System:
Other Numbering System NameOther Numbering System ID
Computer Science Technical Report3340
Record Number:CaltechCONF:20120504-144406140
Persistent URL:http://resolver.caltech.edu/CaltechCONF:20120504-144406140
Related URLs:
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:181
Collection:CaltechCONF
Deposited By: Kristin Buxton
Deposited On:08 Aug 2012 20:12
Last Modified:26 Dec 2012 07:10

Repository Staff Only: item control page