CaltechCONF
  A Caltech Library Service

Self-Timed VLSI Systems

Seitz, Charles L. (1979) Self-Timed VLSI Systems. In: Proceedings of the Caltech Conference On Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 345-355. http://resolver.caltech.edu/CaltechCONF:20120504-144846690

[img]
Preview
PDF - Published Version
See Usage Policy.

2260Kb

Use this Persistent URL to link to this item: http://resolver.caltech.edu/CaltechCONF:20120504-144846690

Abstract

This short paper is intended to explain why the subject of self-timed logic is relevant to a conference on VLSI. Scaling down feature size and scaling up chip area not only increases the complexity of chips, but also changes relationships in the parameters which describe the physical characteristics of switching devices, circuits, and wires. The physical change which most impacts the design disciplines employed for VLSI -- particularly the timing aspect of design -- is the increased wire delay associated with the increased resistivity of scaled down wires. Wires that run even a small fraction of the way across a chip will impose a significant delay. Clock distribution and long-distance communication required by synchronous systems will become problematic. Otherwise, it appears that the timing aspect of design for submicron feature size circuits will generally resemble that of today's MOS technology, in that delays will be largely determined by parasitic wiring capacitance.


Item Type:Book Section
Additional Information:This research was supported by the Defense Advanced Research Projects Agency (ARPA) under contract number N00123-78-C-0806.
Funders:
Funding AgencyGrant Number
Defense Advanced Research Projects AgencyN00123-78-X-0806
Other Numbering System:
Other Numbering System NameOther Numbering System ID
Computer Science Technical Report3340
Record Number:CaltechCONF:20120504-144846690
Persistent URL:http://resolver.caltech.edu/CaltechCONF:20120504-144846690
Related URLs:
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:182
Collection:CaltechCONF
Deposited By: Kristin Buxton
Deposited On:08 Aug 2012 21:02
Last Modified:26 Dec 2012 07:10

Repository Staff Only: item control page