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Synchronization Strategies

Stucki, M. J and Cox, J. R, Jr. (1979) Synchronization Strategies. In: Proceedings of the Caltech Conference On Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 375-393. http://resolver.caltech.edu/CaltechCONF:20120504-163401189

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Abstract

Computing systems are now frequently composed of independently clocked subsystems that cooperate to perform the function desired for the whole. This type of architecture has many advantages and promises to be the standard for the forseeable future. With the trend towards more and more gates per chip, the number of chips per subsystem gets smaller and smaller, and we can expect to soon see one or more subsystems per chip. This transition will require contributions from disciplines previously outside the field of chip design, and every issue will have to be carefully worked out beforehand because debugging chips of this complexity is a difficult and costly task. This paper addresses one of those issues - the design of reliable synchronization logic for interfacing independently clocked subsystems. The design of this logic is not a normal exercise in clocked logic design because the operating environment is such that the response times of some flipflops will be unbounded, and an improper appreciation of this phenomenon can result in designs plagued by intermittent synchronization failures . The absence of a bound has been documented in the literature, but only from an experimental and analytic standpoint, and no generally applicable methodology for dealing with it has been suggested. As a result, it is not common knowledge among logic designers, and future systems are liable to suffer from it. The objective of this paper is to assist the logic designer by reviewing the basic phenomenon, characterizing it quantitatively, and presenting techniques for coping with it.


Item Type:Book Section
Additional Information:This work has been supported in part by the Division of Research Resources of the National Institutes of Health under Grant RR 00396.
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NIH Division of Research ResourcesRR 00396
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Computer Science Technical Report3340
Record Number:CaltechCONF:20120504-163401189
Persistent URL:http://resolver.caltech.edu/CaltechCONF:20120504-163401189
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:199
Collection:CaltechCONF
Deposited By: Kristin Buxton
Deposited On:08 Aug 2012 18:31
Last Modified:26 Dec 2012 07:10

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