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Trends in Silicon Processing

Rideout, V. Leo (1981) Trends in Silicon Processing. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 65-110.

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The advent of very large scale integration will require substantial progress in all aspects of silicon technology: processing, lithography, modeling, design tools, chip architecture, and applications This paper will survey current trends in silicon integrated circuit fabrication, focusing on new developments and outstanding problems. Progress in both bipolar and MOSFET technologies will be considered. Silicon fabrication techniques will be described in terms of the repetitious application of operations that are additive (oxidation, doping, deposition), selective (lithography), and subtractive (etching). The objective of these operations is a reliable and predictable device structure. Device structures will be described in terms of isolation areas, devices, contacts (intraconnection vias), wiring (interconnection lines), and passivation. Immediate problems in isolation size, device performance, contact resistance, and wiring topography will be identified. Future needs for improved structures will be indicated. Promising new approaches such as lightly-doped drain FETs and silicide-on-polysilicon (polycide) wiring will be described. Throughout this discussion the importance of process modeling will be emphasized.

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Record Number:CaltechCONF:20120507-115627174
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ID Code:201
Deposited By: Kristin Buxton
Deposited On:09 May 2012 17:15
Last Modified:03 Oct 2019 22:50

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