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A Simple Two-Layer Aluminum Metal Process for VLSI

Huber, Robert J. (1979) A Simple Two-Layer Aluminum Metal Process for VLSI. In: Proceedings of the Caltech Conference On Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 113-123. http://resolver.caltech.edu/CaltechCONF:20120507-115757571

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Abstract

The use of two levels of metal interconnect lines in an integrated circuit chip layout is a very desirable feature that allows higher density and greater freedom in the placement of the active components. In spite of these benefits it has often been avoided in the design of integrated circuits. For many applications the cost of the extra processing steps is not justified. In the case of MOS technology, long diffusion runs can be successfully used. In silicon gate MOS the polycrystalline silicon itself provides, with some restrictions, a second level of signal interconnect lines. However other technologies, for example I^2L, need a second layer of low-resistance metal interconnect to effectively utilize the chip area. While conceptually simple, two-layer metal processes have proved to be quite difficult to implement. This paper describes a relatively simple two-layer metal process that is well suited to university laboratories and others with limited facilities.


Item Type:Book Section
Additional Information:This work was carried out at the University of Utah Research Institute Microcircuits Laboratory with support from General Instrument Corporation.
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General Instrument CorporationUNSPECIFIED
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Computer Science Technical Report3340
Record Number:CaltechCONF:20120507-115757571
Persistent URL:http://resolver.caltech.edu/CaltechCONF:20120507-115757571
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:202
Collection:CaltechCONF
Deposited By: Kristin Buxton
Deposited On:07 Aug 2012 22:52
Last Modified:26 Dec 2012 07:10

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