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Silicon Compilation - A Hierarchical Use of PLAs

Ayres, Ron (1979) Silicon Compilation - A Hierarchical Use of PLAs. In: Proceedings of the Caltech Conference On Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 311-326. http://resolver.caltech.edu/CaltechCONF:20120507-120348531

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Abstract

This paper proposes a way to compile a silicon layout directly from synchronous logic specification. The motivation for introducing compilation into the silicon world comes from its extreme success in the software world. As we see silicon area increasing and circuit complexity increasing, we might feel much in common with the early day programmers who faced increasing memory availability along with increasing program complexity.


Item Type:Book Section
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Computer Science Technical Report3340
Record Number:CaltechCONF:20120507-120348531
Persistent URL:http://resolver.caltech.edu/CaltechCONF:20120507-120348531
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:204
Collection:CaltechCONF
Deposited By: Kristin Buxton
Deposited On:07 Aug 2012 22:50
Last Modified:26 Dec 2012 07:10

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