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Characterization and Scaling of MOS Flip Flop Performance in Synchronizer Applications

Chaney, Thomas J. and Rosenberger, Fred U. (1979) Characterization and Scaling of MOS Flip Flop Performance in Synchronizer Applications. In: Proceedings of the Caltech Conference On Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 357-374. http://resolver.caltech.edu/CaltechCONF:20120507-124118999

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Abstract

The measured and calculated values of t he Flip Flop parameters needed to specify synchronizer reliability are presented for 3 different depletion-load, silicon gate, NMOS, R-S Flip Flop circuits with gate lengths ranging from 6μm to 4.2μm. Estimates of the probability of synchronizer failure to resolve within allowed or desired times can be determined from these parameters.


Item Type:Book Section
Additional Information:This work has been supported by the Division of Research Resources of the National Institutes of Health under Grant RR-00396.
Funders:
Funding AgencyGrant Number
National Institutes of HealthRR-00396
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Computer Science Technical Report3340
Record Number:CaltechCONF:20120507-124118999
Persistent URL:http://resolver.caltech.edu/CaltechCONF:20120507-124118999
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:209
Collection:CaltechCONF
Deposited By: Kristin Buxton
Deposited On:07 Aug 2012 16:59
Last Modified:26 Dec 2012 07:10

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