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Special Purpose Hardware for Design Rule Checking

Seiler, Larry (1981) Special Purpose Hardware for Design Rule Checking. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 197-216. http://resolver.caltech.edu/CaltechCONF:20120507-152701606

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Abstract

Special purpose hardware can significantly increase the speed of integrated circuit design rule checking. The architecture described in this paper uses four custom chips to implement a raster scan DRC algorithm. It allows the use of 45° angles and can be programmed to check a wide variety of design rules involving an arbitrary number of layers. A shrink/expand operation allows the use of rasterization grids that are small relative to the minimum feature size. Using the Mead/Conway NMOS design rules and assuming a grid size of 1/2λ or 1/4 the minimum transistor width, this hardware can completely check a 3000λx3000λ layout in under a minute, if the input data can be provided quickly enough.


Item Type:Book Section
Additional Information:This research was supported in part by United States Air Force Contract AFOSR-F49620-80-C-0073 and the Real Time Systems Group of the MIT Laboratory for Computer Science.
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Funding AgencyGrant Number
United States Air ForceAFOSR-F49620-80-C-0073
Record Number:CaltechCONF:20120507-152701606
Persistent URL:http://resolver.caltech.edu/CaltechCONF:20120507-152701606
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:211
Collection:CaltechCONF
Deposited By: Kristin Buxton
Deposited On:06 Aug 2012 23:05
Last Modified:26 Dec 2012 07:10

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