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PLA Design in NAND Structure

Lin, Chong Ming (1981) PLA Design in NAND Structure. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 343-354. http://resolver.caltech.edu/CaltechCONF:20120507-154030220

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Abstract

A NAND (serial gating) structure PLA of the MOS poly-silicon gate process has been developed for high density and medium fast speed VLSI application. Dynamic clocking is used for minimum power dissipation and elimination of the ratio problem associated with static NAND gate. Ion-implantation for memory cell programming and the elimination of contact in the memory area drastically reduces the cell size, and reliability is improved . A simple but effective self-timed clocking scheme is employed for better operating margins against process variations; the overhead chip area for the clock generation is sufficiently small. The advantages of allowing metal signal and power lines to cross the PLA memory area is discussed. Some measured data from a 3.5μm NMOS Si-gate process with regard to gate height and transistor sizes are also described.


Item Type:Book Section
Additional Information:The author would like to thank those whose contribution and help made this work possible. L. Nguyen --His request for development of an advanced VLSI Chip. D. Morgan Tuan H.T. (BURROUGHS) --Their technical evaluation and encouragement. J. Zeh --His vision and commitment on the project. J. Schneider --His decision, funding and continuous support. T. Northrup, K. Slater, and F. Zereski --Their continuous encouragement and support.
Record Number:CaltechCONF:20120507-154030220
Persistent URL:http://resolver.caltech.edu/CaltechCONF:20120507-154030220
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:215
Collection:CaltechCONF
Deposited By: Kristin Buxton
Deposited On:08 Aug 2012 16:52
Last Modified:26 Dec 2012 07:10

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