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Two Timing Samplers

Frank, Edward H. and Sproull, Robert F. (1981) Two Timing Samplers. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 127-134. http://resolver.caltech.edu/CaltechCONF:20120508-102909138

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Abstract

Testing VLSl chips presents a variety of problems. some of which can be solved by building on-chip testing structures. On-chip testing structures can allow a designer to test aspects of a circuit which might be difficult to test even with expensive test equipment and moreover can provide reasonable testing hardware to designers who do not have access to sophisticated off-chip testing equipment. In this paper we describe a type of on-chip test structure called H timing sampler which enables the designer to accurately measure when on-chip signal transitions occur. The timing samplers we present are simple. They have been fabricated as part of a multi-project chip and experimental results show that they arc reasonably accurate as well.


Item Type:Book Section
Additional Information:This research was sponsored by the Defense Advanced Research Projects Agency (DOD). ARPA Order No. 3597. monitored by the Air Force Avionics Laboratory Under Contract F33615-78-C-1551. The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied. of the Defense Advanced Research Projects Agency or the US Government.
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Funding AgencyGrant Number
Defense Advanced Research Projects AgencyARPA Order 3597
Air Force Avionics LaboratoryF33615-78-C-1551
Record Number:CaltechCONF:20120508-102909138
Persistent URL:http://resolver.caltech.edu/CaltechCONF:20120508-102909138
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:222
Collection:CaltechCONF
Deposited By: Kristin Buxton
Deposited On:07 Aug 2012 16:51
Last Modified:26 Dec 2012 07:10

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