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Systolic Priority Queues

Leiserson, Charles E. (1979) Systolic Priority Queues. In: Proceedings of the Caltech Conference On Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 199-214.

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Very large scale integrated (VLSI) circuit technology has made it possible to build multiprocessor hardware devices to aid in the rapid solution of sophisticated problems. An algorithms designer wishing to take full advantage of the massive parallelism offered by VLSI must address geometric issues hitherto relegated to layout artists. The reason for this is that VLSI is a planar technology in which the interconnections among components on a chip may cost more than the components themselves. The designer of a multiprocessor algorithm to be implemented in this technology must consider the complexity of the data paths between processors in evaluating the algorithm.

Item Type:Book Section
Additional Information:Copyright -c- 1979 by Charles E. Leiserson. This research is supported in part by the National Science Foundation under Grant MCS 75-222-55, the Office of Naval Research under Contract N00014-76-c-o370, NR 044-422, and by the Fannie and John Hertz Foundation.
Funding AgencyGrant Number
NSFMCS 15-222-55
Office of Naval ResearchN00014-76-C-0370
Office of Naval ResearchNR 044-422
Fannie and John Hertz FoundationUNSPECIFIED
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Computer Science Technical Report3340
Record Number:CaltechCONF:20120503-130458130
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:173
Deposited By: Kristin Buxton
Deposited On:08 Aug 2012 21:04
Last Modified:03 Oct 2019 22:50

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