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Self-Timed VLSI Systems

Seitz, Charles L. (1979) Self-Timed VLSI Systems. In: Proceedings of the Caltech Conference On Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 345-355.

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This short paper is intended to explain why the subject of self-timed logic is relevant to a conference on VLSI. Scaling down feature size and scaling up chip area not only increases the complexity of chips, but also changes relationships in the parameters which describe the physical characteristics of switching devices, circuits, and wires. The physical change which most impacts the design disciplines employed for VLSI -- particularly the timing aspect of design -- is the increased wire delay associated with the increased resistivity of scaled down wires. Wires that run even a small fraction of the way across a chip will impose a significant delay. Clock distribution and long-distance communication required by synchronous systems will become problematic. Otherwise, it appears that the timing aspect of design for submicron feature size circuits will generally resemble that of today's MOS technology, in that delays will be largely determined by parasitic wiring capacitance.

Item Type:Book Section
Additional Information:This research was supported by the Defense Advanced Research Projects Agency (ARPA) under contract number N00123-78-C-0806.
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Defense Advanced Research Projects AgencyN00123-78-X-0806
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Computer Science Technical Report3340
Record Number:CaltechCONF:20120504-144846690
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:182
Deposited By: Kristin Buxton
Deposited On:08 Aug 2012 21:02
Last Modified:03 Oct 2019 22:50

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