Lea, R. M. and Sreetharan, M. (1979) WSI Distributed Logic Memories. In: Proceedings of the Caltech Conference On Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 187-197. https://resolver.caltech.edu/CaltechCONF:20120504-160132955
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Abstract
Wafer-Scale Intearation (WSI) offers the possibility of departing from the von Naumann computer architecture and alleviating its implementation problems. By interconnecting the good chips on an undiced wafer, WSI provides a multiplicity of processing elements and bypasses the expensive stages of chip and printed circuit board manufacture. Whereas VLSI offers low-cost components at the sub-system level, WSI offers low-cost computer systems . Hence, traditional market pressures deter the speculative development of a range of VLSI chips in order to launch a radically new computer structure. However, WSI offers the integration of a new architecture in a single development.
Item Type: | Book Section | ||||||
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Additional Information: | The authors gratefully acknowledge the support of ACTP (Department of Industry) and the many fruitful discussions with R. C. Aubusson, I. Catt and E.A. Newman. | ||||||
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Record Number: | CaltechCONF:20120504-160132955 | ||||||
Persistent URL: | https://resolver.caltech.edu/CaltechCONF:20120504-160132955 | ||||||
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Usage Policy: | No commercial reproduction, distribution, display or performance rights in this work are provided. | ||||||
ID Code: | 190 | ||||||
Collection: | CaltechCONF | ||||||
Deposited By: | Kristin Buxton | ||||||
Deposited On: | 08 Aug 2012 17:51 | ||||||
Last Modified: | 03 Oct 2019 22:50 |
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