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The Torus: An Exercise in Constructing a Processing Surface

Martin, Alain J. (1981) The Torus: An Exercise in Constructing a Processing Surface. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 527-537. https://resolver.caltech.edu/CaltechCONF:20120507-152709316

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Abstract

A "Processing Surface" is defined as a large, dense, and regular arrangement of processor and storage modules on a two-dimensional surface, e.g. a VLSI chip. A general method is described for distributing parallel recursive computations over such a surface. Scope rules enforcing the "locality" of variables and procedure parameters are introduced in the programming language. These rules and a particular interconnection of the modules on the surface make it possible to transmit parameter and variable values between modules without using extraneous communication actions. The choice of the Processing Surface topology for binary recursive computations is discussed and a torus-like topology is chosen.


Item Type:Book Section
Additional Information:The first torus machine was built at the beginning of 1979 at Philips Research Laboratories. It is a twisted torus of 36 cells. Each cell consists of two INTEL chips (one processor with a 1K byte ROM, and one 256 byte RAM.). It is not a Processing Surface but a network of machines communicating by explicit message exchanges. Acknowledgement is due to W.J. Lippmann and G.A. Slavenburg for their invaluable cooperation during the construction of this machine. Without their hardware and software competence, it would never have been completed within such a short term. The fact that it was completed within 3 months is also a consequence of the regularity of the structure. Acknowledgement is also due to C.S. Scholten for several valuable comments on the first paper on the subject [3], and to Alan Davis whose comments on the manuscript led to many improvements.
Record Number:CaltechCONF:20120507-152709316
Persistent URL:https://resolver.caltech.edu/CaltechCONF:20120507-152709316
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ID Code:212
Collection:CaltechCONF
Deposited By: Kristin Buxton
Deposited On:08 Aug 2012 17:14
Last Modified:03 Oct 2019 22:50

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