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Algorithmic Layout of Gate Macros

Gajski, Daniel D. and Bilgory, Avinoam and Luhukay, Joseph (1981) Algorithmic Layout of Gate Macros. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 237-252.

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This paper describes the basic modules of a gate-to-silicon compiler which accepts as its input a high level description of gate macros and generates a layout that satisfies particular technology (NMOS, for example) and environmental parameters (layout area or time delay, for example).

Item Type:Book Section
Additional Information:This work was supported in part by the NSF under grant No. US NSF MCS80-0156l.
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Record Number:CaltechCONF:20120507-160905572
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:218
Deposited By: Kristin Buxton
Deposited On:08 Aug 2012 16:50
Last Modified:03 Oct 2019 22:50

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