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A One Transistor RAM for MPC Projects

Cherry, James J. and Roylance, Gerald L. (1981) A One Transistor RAM for MPC Projects. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 329-341.

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Many MPC projects, such as video frame buffers, need a large memory subsystem. A one transistor per bit dynamic memory using Mead-Conway design rules is being designed with this purpose in mind. The memory cell size is 16.5 λ by 8λ (about the same size as a 1975 4K RAM cell with λ = 2.5 microns). While a complete high density memory subsystem has not been designed, two chips have been designed to test its major components. One chip is a 1K memory array that tests the sense amplifier, column decoder/driver, and read/write logic. This chip lacks a timing generator and clock drivers. The second chip tests some low power bootstrapped clock drivers. These test chips are currently being fabricated.

Item Type:Book Section
Additional Information:This report describes research done at the Artificial Intelligence Laboratory of the Massachusetts Institute of Technology. Support for the Laboratory's V. L. S. I. research is provided in part by the Advanced Research Projects Agency of the Department of Defense under Office of Naval Research Contract number N00014-80-C-00622 and in part by the Advanced Research Projects Agency under Office of Naval Research contract N00014-75-C-0643.
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Advanced Research Projects AgencyN00014-80-C-0622
Advanced Research Projects AgencyN00014-75-C-0643
Record Number:CaltechCONF:20120508-103916312
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:227
Deposited By: Kristin Buxton
Deposited On:06 Aug 2012 23:49
Last Modified:03 Oct 2019 22:50

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