Liu, K. Y. (1981) Architecture for VLSI Design of Ree-Solomon Encoders. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 539-553. https://resolver.caltech.edu/CaltechCONF:20120508-113437359
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Abstract
In this paper, the logic structure of a universal VLSI chip called the symbol-slice Reed-Solomon (RS) encoder chip is presented. An RS encoder can be constructed by cascading and properly interconnecting a group of such VLSI chips. As a design example, it is shown that a (255,223) RS encoder requiring around 40 discrete CMOS IC's may be replaced by an RS encoder consisting of four identical interconnected VLSI RS encoder chips. Besides the size advantage, the VLSI RS encoder also has the potential advantages of requiring less power and having a higher reliability.
| Item Type: | Book Section | ||||||
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| Additional Information: | This paper presents one phase of research conducted at the Jet Propulsion Laboratory , California Institute of Technology under contract No. NAS-7-100 sponsored by the National Aeronautics and Space Administration. | ||||||
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| Record Number: | CaltechCONF:20120508-113437359 | ||||||
| Persistent URL: | https://resolver.caltech.edu/CaltechCONF:20120508-113437359 | ||||||
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| Usage Policy: | No commercial reproduction, distribution, display or performance rights in this work are provided. | ||||||
| ID Code: | 229 | ||||||
| Collection: | CaltechCONF | ||||||
| Deposited By: | Kristin Buxton | ||||||
| Deposited On: | 06 Aug 2012 23:06 | ||||||
| Last Modified: | 03 Oct 2019 22:50 |
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