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A Methodology for Improved Verification of VLSI Designs without Loss of Area

Scheffer, Louis K. (1981) A Methodology for Improved Verification of VLSI Designs without Loss of Area. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 299-309.

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This paper describes an IC layout methodology based on arbitrary outline cells, prevention of overlap, and mixed programs and graphics. Advantages are: no loss in area over hand packing; incremental checking of design rules, component interconnection, and timing; reduction of visible complexity; and easy implementation. Disadvantages are: possible proliferation of cell types and poor handling of cells with contacts not on the boundary. An implementation that uses and enforces this methodology is discussed.

Item Type:Book Section
Additional Information:i would like to thank the design aids group at Hewlett-Packard for supporting this work, and my colleagues at Stanford University for many fruitful discussions. Martin Newell suggested including the analogy to structured programming.
Record Number:CaltechCONF:20120508-134713504
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:231
Deposited By: Kristin Buxton
Deposited On:09 May 2012 23:22
Last Modified:03 Oct 2019 22:50

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