Penfield, Paul, Jr. and Rubinstein, Jorge (1981) Signal Delay in RC Tree Networks. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 269-283. https://resolver.caltech.edu/CaltechCONF:20120508-141912762
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Abstract
In MOS integrated circuits, signals may propagate between stages with fanout. The exact calculation of signal delay through such networks is difficult. However, upper and lower bounds for delay that are computationally simple are presented in this paper. The results can be used (1) to bound the delay, given the signal threshold; or (2) to bound the signal voltage, given a delay time; or (3) to certify that a circuit is "fast enough", given both the maximum delay and the voltage threshold.
| Item Type: | Book Section | ||||||||
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| Additional Information: | This work was supported in part by Digital Equipment Corporation, in part by the Advanced Research Projects Agency of the Department of Defense and monitored by the Office of Naval Research under Contract N00014-C-80-0622, and in part by the Air Force under Contract Number AFOSR 4-9620-80-0073. | ||||||||
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| Record Number: | CaltechCONF:20120508-141912762 | ||||||||
| Persistent URL: | https://resolver.caltech.edu/CaltechCONF:20120508-141912762 | ||||||||
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| Usage Policy: | No commercial reproduction, distribution, display or performance rights in this work are provided. | ||||||||
| ID Code: | 237 | ||||||||
| Collection: | CaltechCONF | ||||||||
| Deposited By: | Kristin Buxton | ||||||||
| Deposited On: | 09 May 2012 17:29 | ||||||||
| Last Modified: | 03 Oct 2019 22:50 |
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