Functional Verification in an Interactive Symbolic IC Design Environment

Abstract

This paper describes verification techniques that have been implemented as part of an interactive symbolic IC design system. Circuit analysis programs perform node extraction and gate decomposition. They generate both transistor and gate level circuit desriptions which are used as input to a transistor level digital MOS timing simulator. The extraction programs make use of an intermediate circuit description language which captures both geometric placement and circuit connectivity. All programs are written in the C programming language and run under the UNIX operating system. An example is included to demonstrate the operation of these various techniques.