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Functional Verification in an Interactive Symbolic IC Design Environment

Ackland, Bryan and Weste, Neil (1981) Functional Verification in an Interactive Symbolic IC Design Environment. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 285-298.

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This paper describes verification techniques that have been implemented as part of an interactive symbolic IC design system. Circuit analysis programs perform node extraction and gate decomposition. They generate both transistor and gate level circuit desriptions which are used as input to a transistor level digital MOS timing simulator. The extraction programs make use of an intermediate circuit description language which captures both geometric placement and circuit connectivity. All programs are written in the C programming language and run under the UNIX operating system. An example is included to demonstrate the operation of these various techniques.

Item Type:Book Section
Record Number:CaltechCONF:20120507-153514157
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:214
Deposited By: Kristin Buxton
Deposited On:08 Aug 2012 16:53
Last Modified:03 Oct 2019 22:50

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