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Electron Beam Testing and Restructuring of Integrated Circuits

Shaver, D. C. (1981) Electron Beam Testing and Restructuring of Integrated Circuits. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 111-126.

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Dramatic improvements in the cost, performance, and reliability of a digital system can he obtained if the system is integrated on a single chip. Many systems are sufficiently complex that the die size resulting from integration would be very large with a low probability of producing a perfect, functioning die. Since there is a real need for larger integrated systems than can be fabricated free of defects, it is likely that techniques which can locate and "wire-around" defects will be useful and will allow the die-size to increase, perhaps to full-wafer size.

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Additional Information:This work was supported by the Department of the Air Force and the Defense Advanced Research Projects Agency. The test chips used for these experiments were fabricated as part of the DARPA sponsored MPC-580 multiproject chip. I would like to thank everyone at Hewlett-Packard, Micro Mask, and Xerox who made this multiproject chip a success. At Lincoln Laboratory, Dr. B. Burke provided test FETs used for initial experiments, and P. Daniels and D. Klays provided assistance with packaging and bonding.
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Department of the Air ForceUNSPECIFIED
Defense Advanced Research Projects AgencyUNSPECIFIED
Record Number:CaltechCONF:20120508-102529066
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ID Code:221
Deposited By: Kristin Buxton
Deposited On:07 Aug 2012 16:52
Last Modified:03 Oct 2019 22:50

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