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Bit-Serial Inner Product Processors in VLSI

Buric, Misha R. and Mead, Carver A. (1981) Bit-Serial Inner Product Processors in VLSI. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 155-164.

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In this paper we describe a bit-serial pipelined implementation of an inner product processor, and related interconnections of a number of such processors on a single chip. We argue that bit-serial computational models are particularly suited for VLSI, because of relatively inexpensive communication links and arithmetic processing elements, in terms of the area occupied on silicon. Sixteen inner product processors, described here, may be easily placed on a single 40-pin chip in today's NMOS technology with a 2 micron lambda. Similar arguments for bitserial arithmetic were used in [3]. in a description of a design of a general purpose massively parallel processor.

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Additional Information:We are grateful to David Hagelbarger for suggesting the structure of the multiplier. Also, we would like to thank Sandy Fraser and Mike Maul for making the chip production possible.
Record Number:CaltechCONF:20120508-140618414
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:235
Deposited By: Kristin Buxton
Deposited On:09 May 2012 19:36
Last Modified:03 Oct 2019 22:50

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