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A Structured Approach to VLSI Layout Design

Krishnan, M. S. (1981) A Structured Approach to VLSI Layout Design. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 413-432. http://resolver.caltech.edu/CaltechCONF:20120508-141651390

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Abstract

A new approach to the VLSI layout problem is proposed that produces a structured floor plan for an arbitrary network of interconnected processing elements. It is based on extracting a minimum spanning tree from a given representation of a computation network and using an efficient, structured layout scheme for this minimum spanning tree. Techniques to lay out trees as arrays of layout slices are presented. It is assumed that the nodes of a network are identical in their layout size and connectivity. This method is valid at any level of a VLSI design since these nodes may represent gates, cells or complex macros. An application of this approach to modified tree networks is described. Other useful applications of the method are mentioned.


Item Type:Book Section
Additional Information:The author is thankful to the Xerox Corporation for their support during this research.
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Xerox CorporationUNSPECIFIED
Record Number:CaltechCONF:20120508-141651390
Persistent URL:http://resolver.caltech.edu/CaltechCONF:20120508-141651390
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:236
Collection:CaltechCONF
Deposited By: Kristin Buxton
Deposited On:09 May 2012 17:31
Last Modified:26 Dec 2012 07:11

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