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A Data-Drive Machine Architecture Suitable for VLSI Implementation

Davis, A. L. (1979) A Data-Drive Machine Architecture Suitable for VLSI Implementation. In: Proceedings of the Caltech Conference On Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 479-494.

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A machine architecture is presented which is capable of supporting very high levels of concurrency. The machine language of the class of machines described here is a graphical program schema known as data-driven nets. The machine architecture is arbitrarily extensible and consists of a recursively organized hierarchy of homogeneous processor-store modules. System control is decentralized, and each module is a completely asynchronous processing site, capable of executing any machine language program. Resource allocation is performed dynamically on the basis of the amount of available concurrency in the program and on the availability of physical resources.

Item Type:Book Section
Additional Information:The work reported in this paper was supported by Burroughs Corporation. DDM1, a prototype module of the architecture described in this paper, is a hard wired data-driven machine, and was completed in July 1976 at the Burroughs Interactive Research Center in La Jolla, California. Many of the early systems ideas were developed in conjunction with Robert S. Barton. Gary Hodgman, Lawrence Rogers, and Karl Boekelheide were instrumental in the conceptualization and implementation of the actual machine. DDM1 now resides at the University of Utah, where the project continues under the support of the Burroughs Corporation.
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Burroughs CorporationUNSPECIFIED
Subject Keywords:VLSI, concurrency, pipelining, recursive hierarchy, data-flow
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Computer Science Technical Report3340
Record Number:CaltechCONF:20120504-133310742
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:174
Deposited By: Kristin Buxton
Deposited On:08 Aug 2012 21:53
Last Modified:03 Oct 2019 22:50

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