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A Subnanosecond LSI Family for Mainframe Technology

Muller, H. H. and Stopper, H. and Tam, R. K. (1979) A Subnanosecond LSI Family for Mainframe Technology. In: Proceedings of the Caltech Conference On Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 105-112. https://resolver.caltech.edu/CaltechCONF:20120504-144406140

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Abstract

A subnanosecond LSI family is defined for next generation mainframes. It employs distributed on-chip regulation to reduce system power supply cost, stacked structures for delay-power improvement, on-chip test/diagnostic monitors and signature circuits to improve system maintainability.


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Record Number:CaltechCONF:20120504-144406140
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:181
Collection:CaltechCONF
Deposited By: Kristin Buxton
Deposited On:08 Aug 2012 20:12
Last Modified:03 Oct 2019 22:50

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