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Timing Considerations in Logic Arrays and Their Importance to Self Timed Digital Circuits

Patil, Suhas S. (1979) Timing Considerations in Logic Arrays and Their Importance to Self Timed Digital Circuits. In: Proceedings of the Caltech Conference On Very Large Scale Integration. California Institute of Technology , Pasadena, CA, p. 428.

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This paper presents a method for the design of self timed circuits on an integrated circuit that takes advantage of certain temporal constraints that are realizable in logic arrays. This method of design recognizes two distinct environments for circuits, the local environment and the global environment and further recognizes that the assumptions regarding the temporal characteristics of the system that may be valid in the local environment may not be valid in the global environment. This paper shows how self timed circuits can be systematically designed on a single chip using assumptions reasonable for components on a single chip. This paper is based on our work on Structured Logic Arrays (SLAs) and first explains the intricacies of the temporal constraints implemented in the structured array and then shows how one can take advantage of these constraints in the design of self timed circuits. In this structure, for example, it is possible to design an asynchronous sequential state machine with non adjacent transitions without getting into hazardous conditions. What is presented is related to Petri nets and their realization in circuits. The circuits that are designed using this method are very regular in structure and are efficient in utilization of chip area. Furthermore, fairly large integrated circuits can be designed relatively fast using this method. Examples of some chip designs are presented.

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Computer Science Technical Report3340
Record Number:CaltechCONF:20120507-120804115
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ID Code:206
Deposited By: Kristin Buxton
Deposited On:07 Aug 2012 22:46
Last Modified:03 Oct 2019 22:50

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