Allen, Phillip E. and Cantrell, William H. (1981) Considerations for an Analog Four Quadrant SC Multiplier. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 313-217. https://resolver.caltech.edu/CaltechCONF:20120508-142315429
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Abstract
This paper outlines the considerations and design of a four quadrant analog multiplier using switched capacitor (SC) techniques. The design algorithm for accomplishing the multiplication is described. Implementation of the algorithm is then presented. The predicted accuracy of the multiplier is given and compared to preliminary breadboard measurements. The multiplier described is presently being fabricated as an integrated circuit on a university multichip project using double-poly MOS technology.
| Item Type: | Book Section | ||||||
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| Record Number: | CaltechCONF:20120508-142315429 | ||||||
| Persistent URL: | https://resolver.caltech.edu/CaltechCONF:20120508-142315429 | ||||||
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| Usage Policy: | No commercial reproduction, distribution, display or performance rights in this work are provided. | ||||||
| ID Code: | 238 | ||||||
| Collection: | CaltechCONF | ||||||
| Deposited By: | Kristin Buxton | ||||||
| Deposited On: | 09 May 2012 17:28 | ||||||
| Last Modified: | 03 Oct 2019 22:50 |
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