Browse by Conference

1981

Buric, Misha R. and Mead, Carver A. (1981) Bit-Serial Inner Product Processors in VLSI. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 155-164. https://resolver.caltech.edu/CaltechCONF:20120508-140618414

Browning, Sally A. and Seitz, Charles L. (1981) Communication in a Tree Machine. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 509-526. https://resolver.caltech.edu/CaltechCONF:20120508-143029685

Allen, Phillip E. and Cantrell, William H. (1981) Considerations for an Analog Four Quadrant SC Multiplier. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 313-217. https://resolver.caltech.edu/CaltechCONF:20120508-142315429

Conway, Lynn A. (1981) THE MPC ADVENTURES: Experiences with the Generation of VLSI Design and Implementation Methodologies. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 5-27. https://resolver.caltech.edu/CaltechCONF:20120508-135204801

Scheffer, Louis K. (1981) A Methodology for Improved Verification of VLSI Designs without Loss of Area. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 299-309. https://resolver.caltech.edu/CaltechCONF:20120508-134713504

Mead, Carver and Rem, Martin (1981) Minimum Propagation Delays in VLSI. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 433-439. https://resolver.caltech.edu/CaltechCONF:20120508-140116957

Tsividis, Yannis P. and Antoniadis, Dimitri A. (1981) A Multiproject Chip Approach to the Teaching of Analog MOS LSI and VLSI. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 355-371. https://resolver.caltech.edu/CaltechCONF:20120508-143716343

Rem, Martin and Mead, Carver (1981) A Notation for Designing Restoring Logic Circuitry in CMOS. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 399-411. https://resolver.caltech.edu/CaltechCONF:20120508-142455789

Budzinski, Rob and Linn, John and Thatte, Satish (1981) A Restructurable Integrated Circuit for Implementing Programmable Digital Systems. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 481-508. https://resolver.caltech.edu/CaltechCONF:20120508-142740335

Buehler, Martin G. and Linholm, Loren W. (1981) The Rolf of Test Chips in Coordinating Logic and Circuit Design and Layout Aids for VLSI. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 135-151. https://resolver.caltech.edu/CaltechCONF:20120508-135820383

Penfield, Paul, Jr. and Rubinstein, Jorge (1981) Signal Delay in RC Tree Networks. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 269-283. https://resolver.caltech.edu/CaltechCONF:20120508-141912762

Krishnan, M. S. (1981) A Structured Approach to VLSI Layout Design. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 413-432. https://resolver.caltech.edu/CaltechCONF:20120508-141651390

Johnsson, Lennart and Weiser, Uri and Cohen, Danny and Davis, Alan L. (1981) Towards a Formal Treatment of VLSI Arrays. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 375-398. https://resolver.caltech.edu/CaltechCONF:20120508-133029898

Rideout, V. Leo (1981) Trends in Silicon Processing. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 65-110. https://resolver.caltech.edu/CaltechCONF:20120507-115627174

Gajski, Daniel D. and Bilgory, Avinoam and Luhukay, Joseph (1981) Algorithmic Layout of Gate Macros. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 237-252. https://resolver.caltech.edu/CaltechCONF:20120507-160905572

Liu, K. Y. (1981) Architecture for VLSI Design of Ree-Solomon Encoders. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 539-553. https://resolver.caltech.edu/CaltechCONF:20120508-113437359

Smith, David R. and Chan, Douglas (1981) Communications for Next Generation single chip computers. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 555-585. https://resolver.caltech.edu/CaltechCONF:20120508-102133034

Shaver, D. C. (1981) Electron Beam Testing and Restructuring of Integrated Circuits. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 111-126. https://resolver.caltech.edu/CaltechCONF:20120508-102529066

Wetlesen, Gunnar A. (1981) Fast Turnaround Fabrication for Custom VLSI. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 45-53. https://resolver.caltech.edu/CaltechCONF:20120508-103555708

Ackland, Bryan and Weste, Neil (1981) Functional Verification in an Interactive Symbolic IC Design Environment. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 285-298. https://resolver.caltech.edu/CaltechCONF:20120507-153514157

Hayes, John P. (1981) A Logic Design Theory for VLSI. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 455-476. https://resolver.caltech.edu/CaltechCONF:20120508-111721911

Hoffman, Gordon B. (1981) Longer Term Directions for Semi-Custom VLSI. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 55-61. https://resolver.caltech.edu/CaltechCONF:20120508-103200574

Cohen, Danny and Lewicki, George (1981) MOSIS - The ARPA Silicon Broker. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 29-44. https://resolver.caltech.edu/CaltechCONF:20120507-161256758

Cherry, James J. and Roylance, Gerald L. (1981) A One Transistor RAM for MPC Projects. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 329-341. https://resolver.caltech.edu/CaltechCONF:20120508-103916312

Lin, Chong Ming (1981) PLA Design in NAND Structure. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 343-354. https://resolver.caltech.edu/CaltechCONF:20120507-154030220

Hennessy, John (1981) SLIM: A Language for Microcode Description and Simulation in VLSI. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 253-267. https://resolver.caltech.edu/CaltechCONF:20120508-103155488

Carroll, Christopher R. (1981) A Smart Memory Array Processor for Two Layer Path Finding. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 165-195. https://resolver.caltech.edu/CaltechCONF:20120507-155151454

Seiler, Larry (1981) Special Purpose Hardware for Design Rule Checking. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 197-216. https://resolver.caltech.edu/CaltechCONF:20120507-152701606

Martin, Alain J. (1981) The Torus: An Exercise in Constructing a Processing Surface. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 527-537. https://resolver.caltech.edu/CaltechCONF:20120507-152709316

Chazelle, B. M. and Monier, L. M. (1981) Towards More Realistic Models of Computation for VLSI. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 441-453. https://resolver.caltech.edu/CaltechCONF:20120507-153058673

Frank, Edward H. and Sproull, Robert F. (1981) Two Timing Samplers. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 127-134. https://resolver.caltech.edu/CaltechCONF:20120508-102909138

Tanner, John E. and Raibert, Marc H. and Eskenazi, Raymond (1981) A VLSI Tactile Sensing Array Computer. In: Proceedings of the Second Caltech Conference on Very Large Scale Integration. California Institute of Technology , Pasadena, CA, pp. 217-233. https://resolver.caltech.edu/CaltechCONF:20120508-103910815